Method of fabricating a field effect transistor structure with abrupt source/drain junctions

ABSTRACT

Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer ( 108 ) adjacent to the vertical sidewalls of the gate electrode ( 106 ), or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

This is a CIP of 09/191,076, filed Nov. 12, 1998, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to metal-oxide-semiconductor field effecttransistors (MOSFET's) and more particularly to transistor structureshaving abrupt junctions, and methods of making same.

2. Background

The trend of integrating more functions on a single substrate whileoperating at ever higher frequencies has existed in the semiconductorindustry for many years. Advances in both semiconductor processtechnology and digital system architecture have aided in producing thesemore highly integrated and faster operating integrated circuits.

The desired result of many recent advances in semiconductor processtechnology has been to reduce the dimensions of the transistors used toform the individual circuits found on integrated circuits. There areseveral well-recognized benefits of reducing the size of transistors. Inthe case of MOSFETs, reducing the channel length provides the capabilityto deliver a given amount of drive current with a smaller channel width.By reducing the width and length of a FET, the parasitic gatecapacitance, which is a function of the area defined by the width andlength can be reduced, thereby improving circuit performance. Similarly,reducing the size of transistors is beneficial in that less area isconsumed for a given circuit, and this allows more circuits in a givenarea, or a smaller, less costly chip, or both.

It has also been well known that MOSFETs can not simply be scaled downlinearly. That is, as the width and length attributes of a MOSFET arereduced, other parts of the transistor, such as the gate dielectric andthe junctions must also be scaled so as to achieve the desiredelectrical characteristics. Undesirable electrical characteristics inMOSFETs due to improper scaling include coupling of the electric fieldinto the channel region and increased subthreshold conduction. Theseeffects are sometimes referred to in this field as short channeleffects.

A number of methods have been developed to form ever more shallowsource/drain junctions for MOSFETs in order to achieve proper scaling.Unfortunately, these very shallow junctions create source/drainextensions that have increased resistivity as compared with deepersource/drain junctions. In longer channel length MOSFETs with deepersource/drain junctions, the source/drain extension resistivity wasnegligible compared to the on-resistance of the MOSFET itself. However,as MOSFET channel lengths decrease into the deep sub-micron region, theincreased source/drain extension resistivity becomes a significantperformance limitation.

What is needed is a field effect transistor structure having very shortchannel length and low source/drain extension resistivity, yet operableto produce high drive currents without suffering from the short channeleffects that produce significant levels of off-state current. What isfurther needed is a method of manufacturing such a structure.

SUMMARY OF THE INVENTION

Briefly, a MOSFET structure includes highly conductive source/drainextensions of a first conductivity type, and super abrupt junctions witha semiconductor body of a second conductivity type.

In a further aspect of the invention, a process for forming a MOSFETincludes removing portions of the substrate to form recesses that areadjacent and partially subjacent a FET gate structure, and back fillingthe recesses with an epitaxial process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-section of a wafer in process showing asubstrate with a gate dielectric formed thereon, and a patterned gateelectrode over the gate dielectric and a spacer layer formed over thesurface of the wafer.

FIG. 2 is a schematic cross-section showing the structure of FIG. 1,after an anisotropic etch of the spacer layer forms thin sidewallspacers, and the gate dielectric not covered by the gate electrode orsidewall spacers is removed.

FIG. 3 is a schematic cross-section showing the structure of FIG. 2,after an isotropic etch removes portions of the substrate, to formrecesses therein, and further showing a portion of the gate electrodeetched away.

FIG. 4 is a schematic cross-section showing the structure of FIG. 3,after the recesses have been back-filled and the gate electrodethickness built up.

FIG. 5 is a schematic cross-section showing the structure of FIG. 4,after a salicidation operation.

FIG. 6 is a schematic cross-section showing the structure of FIG. 3,after an alternative process flow in which the back-filling of therecesses includes forming a layer of a first conductivity type followedby formation of a layer of a second conductivity type.

FIG. 7 is a flow diagram illustrating the various operations in amanufacturing process in accordance with the present invention.

DETAILED DESCRIPTION

Overview

Conventional source/drain junction formation is accomplished by an ionimplantation operation that is self-aligned to the gate electrode, oralternatively, aligned to sidewall spacers that are adjacent to the gateelectrode. Reasonable transistor performance has been achieved in thisway for many generations of semiconductor process technology. However,as transistor scaling has brought FET channel lengths down into the deepsub-micron region, the changes to source/drain junction depth and dopingconcentration required to achieve desirable electrical performance ofFETs have increased the parasitic resistance associated with the FETsource/drain terminals to the point where this parasitic resistance issignificant compared to the on-resistance of the FET. In this field, theparasitic resistance is sometimes referred to as external resistance.More particularly, simultaneously obtaining the very shallow junctiondepth, high source-drain extension doping concentration, and abruptchange in doping profile between the body and source/drain junctions,all required for desirable electrical performance in deep submicron FETshas become extremely difficult to achieve with conventional processes.

An illustrative embodiment of the present invention provides a FET withhighly conductive source/drain extensions and abrupt junctions. Methodsof forming the FET structure of the present invention includeisotropically etching the substrate adjacent to, and partiallyunderneath, the gate dielectric layer of a FET, and selectivelydepositing bilayers of in-situ doped material of a first conductivitytype, and a second conductivity type.

FETs embodying the present invention include back-filled source anddrain terminals. In this way, the doping concentration of thesource/drain terminals can be controlled by controlling the gas mixture,temperature, and pressure, in a reaction chamber. With the precisecontrol of doping concentration of the material being deposited, theembodiments of the present invention include microelectronic deviceshaving very abrupt junctions. Furthermore, particular embodiments of thepresent invention may eliminate high-energy ion implantation of thesource/drain Junctions. Formation of the source/drain junctions in thisway also provides increased margin for the process thermal budget, sincea high temperature operation is not required to activate the dopants, orto thermally in-diffuse the dopants into the tip portion of thesource/drain terminals.

Terminology

The terms, chip, integrated circuit, monolithic device, semiconductordevice, and microelectronic device, are often used interchangeably inthis field. The present invention is applicable to all the above as theyare generally understood in the field.

The terms metal line, trace, wire, conductor, signal path and signalingmedium are all related. The related terms listed above, are generallyinterchangeable, and appear in order from specific to general. In thisfield, metal lines are sometimes referred to as traces, wires, lines,interconnect or simply metal. Metal lines, generally aluminum (Al),copper (Cu) or an alloy of Al and Cu, are conductors that provide signalpaths for coupling or interconnecting, electrical circuitry. Conductorsother than metal are available in microelectronic devices. Materialssuch as doped polysilicon, doped single-crystal silicon (often referredto simply as diffusion, regardless of whether such doping is achieved bythermal diffusion or ion implantation), titanium (Ti), molybdenum (Mo),cobalt (Co), nickel (Ni) and tungsten (W) and refractory metal suicidesare examples of other conductors.

The terms contact and via, both refer to structures for electricalconnection of conductors from different interconnect levels. These termsare sometimes used in the art to describe both an opening in aninsulator in which the structure will be completed, and the completedstructure itself. For purposes of this disclosure contact and via referto the completed structure.

Epitaxial layer refers to a layer of single crystal semiconductormaterial.

The term “gate” is context sensitive and can be used in two ways whendescribing integrated circuits. As used herein, gate refers to theinsulated gate terminal of a three terminal FET when used in the contextof transistor circuit configuration, and refers to a circuit forrealizing an arbitrary logical function when used in the context of alogic gate. A FET can be viewed as a four terminal device when thesemiconductor body is considered.

Polycrystalline silicon is a nonporous form of silicon made up ofrandomly oriented crystallites or domains. Polycrystalline silicon isoften formed by chemical vapor deposition from a silicon source gas orother methods and has a structure that contains large-angle grainboundaries, twin boundaries, or both. Polycrystalline silicon is oftenreferred to in this field as polysilicon, or sometimes more simply aspoly.

Source/drain terminals refer to the terminals of a FET, between whichconduction occurs under the influence of an electric field, subsequentto the inversion of the semiconductor surface under the influence of anelectric field resulting from a voltage applied to the gate terminal.Source/drain terminals are typically formed in a semiconductor substrateand have a conductivity type (i.e., p-type or n-type) that is theopposite of the conductivity type of the substrate. Sometimes,source/drain terminals are referred to as junctions. Generally, thesource and drain terminals are fabricated such that they aregeometrically symmetrical. Source/drain terminals may includeextensions, sometimes referred to as tips, which are shallower thanother portions of the source/drain terminals. The tips typically extendtoward the channel region of a FET, from the main portion of thesource/drain terminal. With geometrically symmetrical source and drainterminals it is common to simply refer to these terminals assource/drain terminals, and this nomenclature is used herein. Designersoften designate a particular source/drain terminal to be a “source” or a“drain” on the basis of the voltage to be applied to that terminal whenthe FET is operated in a circuit.

Substrate, as used herein, refers to the physical object that is thebasic workpiece that is transformed by various process operations intothe desired microelectronic configuration. A substrate may also bereferred to as a wafer. Wafers, may be made of semiconducting,non-semiconducting, or combinations of semiconducting andnon-semiconducting materials.

The term vertical, as used herein, means substantially perpendicular tothe surface of a substrate.

Referring to FIGS. 1-6, an illustrative embodiment of the presentinvention is described. As shown in,FIG. 1, a wafer is processed inknown ways to form a thin film layer over a patterned gate electrode andover a gate dielectric layer that has been disposed on the top surfaceof the wafer. More particularly, as shown in FIG. 1, a substrate 102 hasa gate dielectric layer 104 disposed over the surface thereof, and apatterned gate electrode 106 is formed over gate dielectric layer 104.In the illustrative embodiment, substrate 102 is a silicon wafer, gatedielectric layer 104 is a silicon dioxide layer, and gate electrode 106is formed from polysilicon. Although gate dielectric layer 104 istypically a thin layer of oxidized silicon, the thickness and chemicalmake-up of the gate insulator layer may be varied within the scope ofthe invention.

Those skilled in the art and having the benefit of this disclosure willrecognize that although field oxide regions are not shown in theFigures, the operations and structures shown and described herein, arecompatible with various field oxide isolation architectures. Examples offield oxide isolation architectures include shallow trench isolationregions in a surface of a substrate, and the older local oxidation ofsilicon, which formed non-planarized oxide isolation regions.

A thin film layer 108 is deposited over the surface of gate electrode106 and the portions of gate dielectric layer 104 not already covered bygate electrode 106. Thin film layer 108 may also be referred to as aspacer layer because spacers adjacent to the side walls of gateelectrode 106 are formed from layer 108 in subsequent processingoperations. It is preferable for spacer layer 108 to have etchcharacteristics that are different from the etch characteristics ofsubstrate 102 and gate electrode 106. The material for spacer layer 108could be any dielectric material including, but not limited to, nitride,oxynitride, and oxide. In the illustrative embodiment, subsequent to thepolysilicon etch that forms gate electrode 106, a thin layer of siliconnitride is deposited over the surface of the substrate to form spacerlayer 108. In one embodiment, the silicon nitride layer is approximately20 nm thick, and is formed in a vertical diffusion furnace. However, thethickness of the nitride layer is not a limitation of the invention andit may be made any practical thickness, for example, in a range of from2 nm to 50 nm thick. This nitride layer will be used to provide theneeded selectivity during a subsequent epitaxial backfill operation.Similarly, the spacer layer may be formed of another material such as,for example, silicon dioxide. Silicon dioxide has a dielectric constantthat is lower than the dielectric constant of silicon nitride, and thisis advantageous in terms of lowering parasitic capacitance between thegate electrode and other nearby circuit nodes.

Referring to FIG. 2, spacer layer 108 is etched anisotropically using,for example, conventional dry etch chemistries for silicon nitride.Subsequent to this etch operation, no significant amount of residualsilicon nitride remains in the source/drain regions. In the illustrativeembodiment, this anisotropic etch operation leaves a nitride layerapproximately 150 nm thick (when measured along a vertical axis) alongthe sidewalls of polysilicon gate electrode 106. Typically, the verticalheight (i.e., thickness) of this layer is approximately equal to thethickness of gate electrode 106. These post-etch nitride structures arereferred to as spacers. As can be seen in FIGS. 1-2, that portion ofsilicon nitride spacer layer 108 that is superjacent to the top surfaceof gate electrode 106 is removed by the spacer layer etch operation.

Referring to FIG. 3, a plurality of recesses in substrate 102 areproduced by using an isotropic dry etch process in a parallel plate RFplasma etching system. A mixture of sulfur hexafluoride (SF₆) and helium(He), at process conditions that favor isotropy are employed. Suchconditions include high pressure and low RF power density. In oneembodiment of the present invention, a process pressure of approximately900 mT, a gap of 1.1 cm, an RF power of 100 W, a He flow of 150 sccm,and a SF₆ flow of 100 sccm is used. RF power may be varied in a range,for example, of 50 W to 200 W, and the process pressure may be variedbut should be greater than approximately 500 mT. This etch process ishighly selective and is characterized by a silicon etch rate that ismuch greater than the etch rate of the silicon dioxide that forms gatedielectric layer 104. Similarly, the etch rate of silicon substrate 102is much greater than the etch rate of the silicon nitride that formssidewall spacers 108. The electrical characteristics of gate dielectriclayer 104 are not adversely affected by the etch process that forms therecesses in substrate 102.

As can be seen in FIG. 3, the recesses include a portion that underliesgate dielectric layer 104. In the illustrative embodiment, substrate 102is etched isotropically such that the lateral etch creates a recessedarea that reaches underneath not only the spacer but also partiallyunderneath a region defined by overlying gate electrode 106.

Note that, since silicon nitride spacer layer 108 was removed from thetop surface of polysilicon gate electrode 106, the etch that forms therecess also etches the top surface of polysilicon gate electrode 106,thereby reducing its height as shown in FIG. 3.

Those skilled in the art and having the benefit of this disclosure willrecognize that the operations and structures disclosed above areapplicable to the formation of both n-channel FETs (NFETs) and p-channelFETs (PFETs). PFETs and NFETs are structurally similar, however therelative placement of p-type and n-type dopants is different. That is, aPFET includes p-type source/drain terminals in an n-type body, and anNFET includes n-type source/drain terminals in a p-type body.

The illustrative embodiment is described in terms of the formation of aPFET. It should be recognized that the present invention applies to thestructure and manufacture of NFETs as well. Referring now to FIG. 4, anepitaxial film of boron doped Si 110 is formed using SiH₂Cl₂ basedchemistry such that the deposition is highly selective to nitride spacer108, i.e., the film of boron doped Si 110 does not form on, nor adhereto, silicon nitride spacer 108. However, the recesses are substantiallyfilled by this deposition operation. The recess may be completely filledby this operation. No ex-situ cleaning operations are performed. This isbecause an external wet clean would tend to damage thin gate dielectriclayer 104. In an alternative embodiment, boron doped SiGe may be used inplace of boron doped Si to form the film that fills the recess.Typically, epitaxial film 110 is deposited such that its top surface isabove the plane of the original surface of substrate 102. This can beseen in FIG. 4 by comparing the relative positions of gate dielectriclayer 104, which was formed on the original surface of substrate 102,with the top surface of Si layer 110. As is further shown in FIG. 4, anepitaxial film of boron doped Si 110 is also formed on top of gateelectrode 106. In this way the thickness of polysilicon gate electrode106 is increased from its post-etch dimensions.

Still referring to FIG. 4, boron doped Si film 110 is formed by aselective deposition. A selective deposition of silicon, or a siliconalloy such as silicon germanium, forms silicon, or the silicon alloy, onthe exposed silicon surfaces. For example, a selective deposition ofboron doped silicon creates Si film 110 on the exposed surfaces ofsilicon substrate 102, and polysilicon gate electrode 106. A siliconfilm can be selectively deposited by heating the wafer to a temperatureof approximately 600° C. to 900° C., providing a deposition gascomprising dichlorosilane (SiH₂Cl₂), and hydrogen (H₂). Moreparticularly, an n-type silicon can be selectively deposited at atemperature of approximately 750° C., with approximately 10 slm H₂,approximately 30 sccm HCl, approximately 100 sccm SiH₂Cl₂, andapproximately 180 sccm PH₃, at approximately atmospheric pressure. Suchprocess conditions can deposit a layer approximately 50 nm thick inapproximately 6 minutes. A p-type silicon can be selectively depositedat a temperature of approximately 800° C., with approximately 20 slm H₂,approximately 70 sccm HCl, approximately 120 sccm SiH₂Cl₂, andapproximately 75 sccm B₂H₆. Such process conditions can deposit a layerapproximately 50 nm thick in approximately 155 seconds.

A silicon germanium alloy can be selectively deposited by heating thewafer to a temperature between approximately 700° C. and 750° C.,providing a deposition gas mix comprising dichlorosilane at a rate ofbetween approximately 10 to 100 sccm, 1% hydrogen diluted germane (GeH₄)at a rate of between approximately 10 to 200 sccm, and hydrogen at arate of approximately 20 slm into a CVD chamber maintained at a pressurebetween approximately 50 to 760 torr. A dopant gas such as diborane,phosphine, or arsine, can be included in the process gas mix if a dopedsilicon or silicon alloy film is desired.

A highly doped (>5×10²⁰ atoms/cm³) n-type silicon germanium epitaxialfilm can be selectively deposited onto silicon surfaces by thermalchemical vapor deposition utilizing a deposition gas mix comprisingapproximately 10 to 200 sccm GeH₄, approximately 10 to 100 sccmdichlorosilane, 10 to 40 slm H₂, 1 to 200 sccm PH₃, and 15 sccm HCl,while maintaining the substrate at a temperature between 700° C. and750° C. and maintaining a deposition pressure of approximately 165 torrduring film deposition. Such a process will form a substantiallyuniformly doped n-type silicon germanium epitaxial film. Similarly, ap-type silicon germanium alloy can be formed by decomposition ofapproximately 20 sccm of dichlorosilane, approximately 80 sccm germane,approximately 20 slm , and a p-type dopant source, such as approximately1-200 sccm of B₂H₆ at a temperature of approximately 740° C. In order toincrease the selectivity of the deposition process, approximately 10sccm of HCl can be added to the gas mix. Such process conditions candeposit a layer approximately 50 nm thick in approximately 75 seconds.

Those skilled in the art and having the benefit of this disclosure, willrecognize that, the deposition operation is such that selectivity tooxide in field oxide regions, or shallow trench isolation regions isalso achieved.

FIG. 5 shows the FET structure of FIG. 4 after further processingoperations are performed. Conventional processing may be used to formadditional sidewall spacers 112 that are disposed along opposingsidewall spacers 108. Furthermore, conventional processing may be usedto form salicided regions 114 over the top surfaces of doped Si regions110, that is, the source/drain extension regions and polysilicon gateelectrode 106. It should be noted that the structure of the presentinvention is advantageous in the formation of salicided source/drainextensions. For example, when a metal such as nickel, which diffuses insilicon relatively easily, is used to form a nickel salicide layer,lateral diffusion of nickel atoms is stopped by nitride side wallspacers 108 and the nickel atoms therefore do not penetrate into thechannel region where they would otherwise adversely affect theelectrical characteristics of the MOSFET. It can be seen in FIG. 4, thatthe thickness of Si 110 and the depth of salicide layer 114 can bevaried with the scope of the invention and still benefit from thestructure's metal atom diffusion barrier characteristics.

Referring to FIG. 6, in a further alternative embodiment of the presentinvention, a layer of phosphorous doped Si 111 is epitaxially formed,prior to an in-situ epitaxial formation of boron doped Si 110. Thoseskilled in the art and having the benefit of this disclosure willappreciate that other n-type dopants may be used in place ofphosphorous. Arsenic is an example of an alternative n-type dopant.

Since the doping concentration of the single crystal epitaxial layer isa function of the gas mixture, temperature, and pressure, in anepitaxial reaction chamber, it is possible to first form a highly dopedSi layer (or Si_(1−x)Ge_(x), x=0 to 0.3) 111 of a first conductivitytype (e.g., n-type by doping with phosphorous). Then without exposingthe wafer to the atmosphere, changing the gas mixture, temperature, andpressure, such that a highly doped Si layer 110 of a second conductivitytype (e.g., p-type by doping with boron) is formed immediatelysuperjacent Si layer 111. In this way, the recesses in substrate 102 arefilled with a bi-layer of single crystal silicon (or Si_(1−x)Ge_(x), x=0to 0.3) having a very abrupt junction.

Desirable electrical characteristics may be obtained in this way byhaving a relatively lightly doped substrate 102 of a first conductivitytype, highly doped source/drain terminals 110 of a second conductivitytype, and a highly doped region 111 of the first conductivity typedisposed between source/drain terminals 110 and lightly doped substrate102. Due to the nature of the selective deposition process (describedabove), highly doped regions 110, 111, are not only highly doped in thesource/drain extension regions, but also in the tip-to-gate overlapregion. The term tip, is generally used to refer to that portion of thesource/drain junction that is subjacent to the gate and adjacent to thechannel portion of a FET.

In conjunction with FIG. 7, the operations of fabricating a FET on awafer in accordance with an illustrative embodiment of the presentinvention are described. An operation (block 202) is performed wherein aspacer layer is formed over a patterned gate electrode. In anillustrative embodiment of the present invention, the gate electrode iscomprised of polysilicon that has previously been deposited over a gatedielectric layer. The gate dielectric is typically oxidized silicon. Inthe illustrative embodiment having an oxide gate dielectric and apolysilicon gate electrode, the spacer layer is typically siliconnitride. Those skilled in the art and having the benefit of thisdisclosure will recognize that the invention is not limited to thecombination of an oxide dielectric and polysilicon gate electrode. Byway of example and not limitation, the gate dielectric layer may consistof an oxide layer and a nitride layer in combination. Similarly, by wayof example and not limitation, the gate electrode may be formed from ametal rather than polysilicon.

After the spacer layer has been formed, it is subjected to ananisotropic etch (block 204) in which sidewall spacers are formed.During the anisotropic etch, portions of the spacer layer that aresuperjacent the top surface the gate electrode and the top surface ofthe wafer are removed. The remaining portion of the spacer layerdisposed along the opposing vertical sidewalls of the gate electrode.

Recesses are formed in the wafer (block 206) at locations where thesource/drain terminals of the FET will be located. The recesses areformed by the isotropic etch of the wafer. As is understood in thisfield, an isotropic etch operation will remove material from the wafersurface both vertically and laterally. The etch chemistry and conditionsare preferably chosen such that the etch is highly selective andpreferentially etches the wafer rather than the side wall spacers or thegate dielectric layer. In the illustrative embodiment, wherein the waferis silicon, the gate dielectric is an oxide of silicon, the gateelectrode is polysilicon and the side wall spacers are silicon nitride,a plasma etch with sulfur hexafluoride (SF₆) and helium (He) is used.

After the recesses are formed, the wafer is typically placed in anepitaxial reactor and a first layer of doped crystalline material isformed (block 208). The crystalline material may be, for example, p-typesilicon, p-type silicon germanium, n-type silicon, or n-type silicongermanium. Typically, the conductivity type of the first layer matchesthe conductivity type of that portion of the wafer where the FET isbeing fabricated. Those skilled in the art will recognize that variousportions of the wafer may be doped and/or counterdoped so as to formwells within which FETs may be formed. For example, n-channel FETs(NFETs) are formed within a p-type region of the wafer, whereasp-channel FETs (PFETs) are formed within an n, type region of the wafer.

After the first layer is formed, a second layer of doped crystallinematerial is formed (block 210). The second layer is typically formedwithout exposing the first layer to the atmosphere. That is, the secondlayer and first layer are formed in a continuous in-situ operation, inthe same reaction chamber simply by changing the gas mixture,temperature, and pressure in the epitaxial reactor. The crystallinematerial may be, for example, p-type silicon, p-type silicon germanium,n-type silicon, or n-type silicon germanium. Typically, the conductivitytype of the second layer is chosen to be opposite that of the firstlayer. In this way, extremely abrupt junctions can be obtained.

For example, a gate structure of a PFET is formed in a region of an-type portion of a silicon wafer, and after the source/drain recessesare formed, a first layer of n-doped (e.g., phosphorous) silicongermanium is formed in the recesses, and then a second layer of p-doped(e.g., boron) silicon germanium is formed over the first layer. Both thefirst and second layers have doping concentrations that aresubstantially higher than the doping concentration of the n-type portionof the silicon wafer, which forms the body terminal of the PFET. Moreparticularly, the first and second layer are substantially free ofcounterdopants, whereas the n-type region of the wafer typicallycontains both n-type and p-type dopants. A gate structure may be a gateelectrode or a gate electrode and adjacent side wall spacers.

A salicidation operation is typically performed to further reduce thesheet resistivity of the source/drain terminals and gate electrode.

Conclusion

Embodiments of the present invention provide a field effect transistorstructure having very short channel length and low source/drainextension resistivity, yet operable to produce high drive currentswithout suffering from the short channel effects that producesignificant levels of off-state current. Further embodiments of thepresent invention provide methods of manufacturing such a structure.

An advantage of particular embodiments of the present invention is thatsource/drain terminals can be formed without annealing. By eliminatingthe high temperature step conventionally required to activate thedopants, thermal diffusion is avoided and the very abrupt junctions aremaintained.

An advantage of particular embodiments of the present invention is thatthe raised junctions formed by back filling, in conjunction with theside wall spacers disposed along opposing vertical walls of the gateelectrode, substantially prevent lateral diffusion of metal atoms in thetransistor channel region during the salicidation operation.

An advantage of particular embodiments of the present invention isplacement of active dopants directly in the tip portion of thesource/drain terminals.

An advantage of particular embodiments of the present invention is thata very precise doping profile is achieved.

An advantage of particular embodiments of the present invention is thatvery shallow, highly doped, source/drain terminals can be formed withoution implantation of the tip portion. In some cases, even a deepsource/drain implant, typically used to form portions of source/drainterminals that lie further from the channel region, may be eliminated.

It will be understood by those skilled in the art having the benefit ofthis disclosure that many design choices are possible within the scopeof the present invention. For example, structural parameters, includingbut not limited to, gate insulator thickness, gate insulator materials,gate electrode thickness, sidewall spacer material, inter-layerdielectric material, isolation trench depth, and S/D and well dopingconcentrations may all be varied from that shown or described inconnection with the illustrative embodiments. Similarly, the operationof forming recesses and back filling with doped crystalline material maybe repeated to tailor the shape and doping profile of the source/drainterminals.

It will be understood that various other changes in the details,materials, and arrangements of the parts and steps which have beendescribed and illustrated may be made by those skilled in the art havingthe benefit of this disclosure without departing from the principles andscope of the invention as expressed in the subjoined Claims.

1. A method of making a junction, comprising: a) forming a gateelectrode on a surface of a substrate, the substrate being of a firstconductivity type; b) isotropically etching the substrate such that arecess in the substrate is formed, the recess including a portion thatunderlies the gate electrode, the recess having a surface; c)selectively forming an epitaxial layer of a first material having thefirst conductivity type over the surface of the recess, and within theportion of the recess that underlies the gate electrode; and d)selectively forming an epitaxial layer of a second material having asecond conductivity type over and within the portion that underlies thegate electrode.
 2. The method of claim 1, wherein the substratecomprises silicon doped to have the first conductivity type; the firstmaterial comprises doped silicon, and the second material comprisesdoped silicon.
 3. The method of claim 1, wherein the substrate comprisessilicon doped to have the first conductivity type; the first materialcomprises doped silicon germanium, and the second material comprisesdoped silicon germanium.
 4. The method of claim 3, wherein the firstmaterial has a thickness that is less than a thickness of the secondmaterial.
 5. The method of claim 4, wherein the second material has atop surface that is above a plane defined by the surface of thesubstrate.
 6. The method of claim 1, wherein the patterned structurecomprises a dielectric layer and a conductive material disposed over thedielectric layer.
 7. The method of claim 1, wherein the etchingpassivates the surface of the recess.
 8. The method of claim 1, whereinetching comprises exposing the substrate to SF₆ and He in an RF plasmaetching system.
 9. The method of claim 1, wherein forming the firstmaterial comprises epitaxially depositing a layer of crystallinematerial.
 10. The method of claim 1, wherein forming the first materialcomprises epitaxially depositing a layer of crystalline material; andforming the second material comprising epitaxially depositing a layer ofcrystalline material; wherein the substrate remains unexposed to theatmosphere subsequent to forming the first material and prior to formingthe second material.